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GATE 2018
Computer OrganizationInstruction PipeliningmediumNAT2 marks
The instruction pipeline of a RISC processor has 5 stages: IF, ID, OF, PO and WB. Stages IF, ID, OF and WB take 1 clock cycle each. Consider a sequence of 100 instructions. In the PO stage, 40 instructions take 3 clock cycles each, 35 instructions take 2 clock cycles each, and 25 instructions take 1 clock cycle each. Assuming no data and control hazards, the number of clock cycles required to complete execution of the 100 instructions is _______
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