If the associativity of a processor cache is doubled while keeping the capacity and block size unchanged, which one of the followi…
Consider a 5-stage pipeline with stage delays of 150 ps, 120 ps, 160 ps, 140 ps, and 110 ps. Assume pipeline register delay is 10 …
An unpipelined processor has a cycle time of 10 ns. A 5-stage pipelined version of the same processor has a clock cycle of 2.5 ns.…
A machine has a 32-bit architecture, with 1-word long instructions. It has 64 registers, each of which is 32 bits long. It needs t…
An access sequence of cache block addresses is of length N and contains n unique block addresses. The number of unique block addre…
Consider two processors P₁ and P₂ executing the same instruction set. Assume that under identical conditions, for the same input, …
Free account benefits
Public PYQs and reference pages stay free. Sign in when you want GATEverse to remember what you studied and guide what to practise next.