GATE 1990
A memory chip has 14 address lines and 8 data lines. What is its capacity in kilobytes (KB)?
In zero-address instruction architectures, operations evaluate expressions using a:
Which memory type is fastest in terms of access latency?
In DMA burst transfer mode, the DMA controller:
Match each addressing mode in List I with the corresponding data element or data-structure element in List II. | List I: Addressi…
Consider a processor P whose instruction set architecture is the load-store architecture. The instruction format is such that the …
Which one of the following dependencies among the register operands of different instructions can cause a data hazard in a pipelin…
Free account benefits
Public PYQs and reference pages stay free. Sign in when you want GATEverse to remember what you studied and guide what to practise next.