GATE 2026 · CS1 - Forenoon
Which one of the following dependencies among the register operands of different instructions can cause a data hazard in a pipelined processor?
Related Computer Organization PYQs
Match each addressing mode in List I with the corresponding data element or data-structure element in List II. | List I: Addressi…
Consider a processor P whose instruction set architecture is the load-store architecture. The instruction format is such that the …
Consider the 8-bit signed integers X, Y and Z represented using the sign-magnitude form. The binary representations of X and Y are…
Consider the real valued variables X, Y and Z represented using the IEEE 754 single-precision floating-point format. The binary re…
The size of the physical address space of a processor is \(2^{32}\) bytes. The capacity of a cache memory unit is \(2^{23}\) bytes…
The EX stage of a pipelined processor performs the memory read operations for LOAD instructions, and the operations for the arithm…
Free account benefits
Turn practice into measurable progress
Public PYQs and reference pages stay free. Sign in when you want GATEverse to remember what you studied and guide what to practise next.
Saved progressKeep answers, mock results and completion history across devices.
Adaptive practiceGet questions matched to your recent accuracy and difficulty level.
Bookmarks and notesBuild a personal revision list and record why a question was difficult.
Performance insightsSee weak subjects, accuracy trends, streaks and exam readiness.