The EX stage of a pipelined processor performs the memory read operations for LOAD instructions, and the operations for the arithmetic and logic instructions. Let tEX denote the time taken by the EX stage to perform the operation for an instruction. For each instruction type, the values of tEX and M (the number of instructions of that type in a sequence of 100 instructions for a program P), are given below: LOAD: tEX=1.8ns, M=15 IMUL: tEX=1.5ns, M=10 IDIV: tEX=2.5ns, M=5 FADD: tEX=1.7ns, M=10 FSUB: tEX=1.7ns, M=5 FMUL: tEX=2.8ns, M=15 FDIV: tEX=3.2ns, M=5 All other instructions: tEX < 1.0ns, M=35 The duration of the pipeline clock cycle is 1 nanosecond. Assume that the latch time for the interstage buffers in the pipeline is negligible. When program P is executed, the number of clock cycles for which the pipeline is stalled due to structural hazards in the EX stage is ______. (answer in integer)