Related Computer Organization PYQs
A 5-stage pipeline with no stalls processes 10 instructions. If each stage takes 1 clock cycle of 10 ns, what is the total executi…
Which bus arbitration scheme uses a centralized bus arbiter where priority is determined dynamically by rotating grants among devi…
Match each addressing mode in List I with the corresponding data element or data-structure element in List II. | List I: Addressi…
Consider a processor P whose instruction set architecture is the load-store architecture. The instruction format is such that the …
Which one of the following dependencies among the register operands of different instructions can cause a data hazard in a pipelin…
Consider the 8-bit signed integers X, Y and Z represented using the sign-magnitude form. The binary representations of X and Y are…
Free account benefits
Turn practice into measurable progress
Public PYQs and reference pages stay free. Sign in when you want GATEverse to remember what you studied and guide what to practise next.