GATE 1992
Which cache architecture guarantees that a memory block can only be placed in exactly one predetermined cache line?
What is the result of adding the two 4-bit two's complement numbers 0101 (+5) and 0011 (+3)?
Programmed I/O requires the CPU to:
In memory-mapped I/O systems, peripheral registers are accessed using:
A cache memory has a hit ratio of 95% (0.95). If cache access time is 10 ns and main memory access time is 100 ns, what is the eff…
Match each addressing mode in List I with the corresponding data element or data-structure element in List II. | List I: Addressi…
Consider a processor P whose instruction set architecture is the load-store architecture. The instruction format is such that the …
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