GATE 2008
Related Computer Organization PYQs
In an instruction execution cycle, the register that holds the address of the next instruction to be fetched from memory is:
Which of the following processor register formats is used in a Zero-Address instruction architecture?
Structural hazards in a processor pipeline occur when:
A direct-mapped cache has 128 cache lines and each line holds 32 bytes. If physical addresses are 32 bits wide, how many bits are …
Match each addressing mode in List I with the corresponding data element or data-structure element in List II. | List I: Addressi…
Consider a processor P whose instruction set architecture is the load-store architecture. The instruction format is such that the …
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