GATE 2008
Related Computer Organization PYQs
In an instruction execution cycle, the register that holds the address of the next instruction to be fetched from memory is:
Which of the following processor register formats is used in a Zero-Address instruction architecture?
What is the decimal equivalent of the binary number (101.101)2?
A direct-mapped cache has 128 cache lines and each line holds 32 bytes. If physical addresses are 32 bits wide, how many bits are …
Match each addressing mode in List I with the corresponding data element or data-structure element in List II. | List I: Addressi…
Consider a processor P whose instruction set architecture is the load-store architecture. The instruction format is such that the …
Free account benefits
Turn practice into measurable progress
Public PYQs and reference pages stay free. Sign in when you want GATEverse to remember what you studied and guide what to practise next.
Saved progressKeep answers, mock results and completion history across devices.
Adaptive practiceGet questions matched to your recent accuracy and difficulty level.
Bookmarks and notesBuild a personal revision list and record why a question was difficult.
Performance insightsSee weak subjects, accuracy trends, streaks and exam readiness.