Match each addressing mode in List I with the corresponding data element or data-structure element in List II. | List I: Addressi…
Consider a processor P whose instruction set architecture is the load-store architecture. The instruction format is such that the …
Which one of the following dependencies among the register operands of different instructions can cause a data hazard in a pipelin…
Consider the 8-bit signed integers X, Y and Z represented using the sign-magnitude form. The binary representations of X and Y are…
Consider the real valued variables X, Y and Z represented using the IEEE 754 single-precision floating-point format. The binary re…
The size of the physical address space of a processor is \(2^{32}\) bytes. The capacity of a cache memory unit is \(2^{23}\) bytes…
Free account benefits
Public PYQs and reference pages stay free. Sign in when you want GATEverse to remember what you studied and guide what to practise next.