Related Computer Organization PYQs
Given the following binary number in 32-bit (single precision) IEEE-754 format: 0 01111100 11011010000000000000000 The decimal val…
In a two-level cache system, the access times of L1 and L2 caches are 1 and 8 clock cycles, respectively. The miss penalty from L2…
Access times and hit ratios: I-cache: 2 ns, hit ratio 0.8; D-cache: 2 ns, hit ratio 0.9; L2-cache: 8 ns, hit ratio 0.9; Main Memor…
Match each addressing mode in List I with the corresponding data element or data-structure element in List II. | List I: Addressi…
Consider a processor P whose instruction set architecture is the load-store architecture. The instruction format is such that the …
Which one of the following dependencies among the register operands of different instructions can cause a data hazard in a pipelin…
Free account benefits
Turn practice into measurable progress
Public PYQs and reference pages stay free. Sign in when you want GATEverse to remember what you studied and guide what to practise next.