GATEverse Practice, past papers & mock tests
GATE 2019
Digital LogicCombinational CircuitsmediumMCQ1 mark
The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has 16 address lines denoted by A15 to A0. What is the range of address (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal?
Save your progress

Related Digital Logic PYQs