Consider a 2-bit saturating up/down counter that performs saturating up-count when (P=0 ) and saturating down-count when (P=1 ). Its next-state table is sh

Question

Consider a 2-bit saturating up/down counter that performs saturating up-count when $P=0$ and saturating down-count when $P=1$. Its next-state table is shown below. The counter is built as a synchronous sequential circuit using D flip-flops.

| $P$ | $Q_1$ | $Q_0$ | $Q_1^+$ | $Q_0^+$ |
| --- | --- | --- | --- | --- |
| 0 | 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 | 1 |
| 0 | 1 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 | 0 |
| 1 | 0 | 1 | 0 | 0 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 0 |

Which one of the following options corresponds to the expressions for the D flip-flop inputs $D_1$ and $D_0$?

Accepted Answer

B. D1 = P'.Q1 + P'.Q0 + Q1.Q0   D0 = P'.Q0' + P'.Q1 + Q1.Q0'

\(P\)	\(Q_1\)	\(Q_0\)	\(Q_1^+\)	\(Q_0^+\)
0	0	0	0	1
0	0	1	1	0
0	1	0	1	1
0	1	1	1	1
1	0	0	0	0
1	0	1	0	0
1	1	0	0	1
1	1	1	1	0

Related Digital Logic PYQs

Turn practice into measurable progress