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GATE 2019
Computer OrganizationMemory OrganizationhardNAT2 marks
A processor deploys a single-level cache with block size of 8 words (4 bytes/word). The memory system uses a 60 MHz clock. To service a cache-miss, the controller takes 1 cycle for address, 3 cycles to fetch all 8 words, and transmits words at 1 word/cycle. The maximum bandwidth for read operations is _______ x 10^6 bytes/sec.
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