GATE 2013 · session-1
Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). Stage delays are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns respectively. Intermediate storage buffers after each stage have delay 1 ns. A program of 12 instructions I1, I2, …, I12 is executed. I4 is the only branch instruction and its target is I9. If the branch is taken, the time (in ns) needed to complete the program is