Sequential Circuits GATE 2005 Question #8441 with Solution

GATE 2005

Digital LogicSequential CircuitseasyMCQ1 mark

In an edge-triggered D flip-flop, the output Q updates:

AOnly during a specific active clock transition (rising or falling edge)BContinuously whenever clock is held at logic highCWhenever the D input changes, regardless of the clockDOnly during power-up

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