GATE 2015 · Set-2
A 4-way set-associative cache memory has a total size of 64 KB with a block size of 32 bytes. If the main memory address is 32 bits, the number of bits in the TAG field is
Related Computer Organization PYQs
For computers based on three-address instruction formats, each address field can be used to specify which of the following: (S1) A…
Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same process…
GATE 2015 CS - Set 2 - Question 18: see question below and answer
GATE 2015 CS - Set 2 - Question 53: see question below and answer
GATE 2015 CS - Set 2 - Question 54: see question below and answer
GATE 2015 CS - Set 3 - Question 34: see question below and answer
Free account benefits
Turn practice into measurable progress
Public PYQs and reference pages stay free. Sign in when you want GATEverse to remember what you studied and guide what to practise next.
Saved progressKeep answers, mock results and completion history across devices.
Adaptive practiceGet questions matched to your recent accuracy and difficulty level.
Bookmarks and notesBuild a personal revision list and record why a question was difficult.
Performance insightsSee weak subjects, accuracy trends, streaks and exam readiness.