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GATE 2021 · Set-1
Computer OrganizationCPU Architecture and Addressing ModeshardNAT2 marks
Consider the following instruction sequence where registers R1, R2 and R3 are general purpose and MEMORY[X] denotes the content at the memory location X. MOV R1, (5000) ; R1 <- MEMORY[5000], size 4 bytes MOV R2, (R3) ; R2 <- MEMORY[R3], size 4 bytes ADD R2, R1 ; R2 <- R1+R2, size 2 bytes MOV (R3), R2 ; MEMORY[R3] <- R2, size 4 bytes INC R3 ; R3 <- R3+1, size 2 bytes DEC R1 ; R1 <- R1-1, size 2 bytes BNZ 1004 ; branch if not zero to given absolute address, size 2 bytes HALT ; stop, size 1 byte Assume that the content of the memory location 5000 is 10, and the content of the register R3 is 3000. The content of each of the memory locations from 3000 to 3010 is 50. The instruction sequence starts from the memory location 1000. All the numbers are in decimal format. Assume that the memory is byte addressable. After the execution of the program, the content of memory location 3010 is _______________.
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