Which one of the following facilitates transfer of bulk data from hard disk to main memory with the highest throughput?

Let R1 and R2 be two 4-bit registers that store numbers in 2's complement form. For the operation R1+R2, which one of the followin…

Let WB and WT be two set associative cache organizations that use LRU algorithm for cache block replacement. WB is a write back ca…

A cache memory that has a hit rate of 0.8 has an access latency 10 ns and miss penalty 100 ns. An optimization is done on the cach…

Consider a system with 2 KB direct mapped data cache with a block size of 64 bytes. The system has a physical address space of 64 …

A processor X1 operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of o…