Memory Management and Virtual Memory GATE 2026 Question #172 with Solution

GATE 2026 · CS1 - Forenoon

Operating SystemsMemory Management and Virtual MemoryhardMSQ2 marks

Consider a system that has a cache memory unit and a memory management unit (MMU). The address input to the cache memory is a physical address. The MMU has a translation lookaside buffer (TLB). Assume that when a page is evicted from the main memory, the corresponding blocks in the cache are marked as invalid. For a given memory reference, which of the following sequences of events can NEVER happen?

ATLB miss, Page table hit, Cache hitBTLB hit, Page table miss, Cache hitCTLB miss, Page table miss, Cache hitDTLB miss, Page table miss, Cache miss

Select every correct option.

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