GATE 2016 · CS1 - Forenoon
Stage delays in a 4-stage pipeline are 800, 500, 400 and 300 ps. The first stage (800 ps) is split into two stages of 600 and 350 ps. The throughput increase of the pipeline is _______ percent.
Related Computer Organization PYQs
The 16-bit 2's complement representation of an integer is 1111 1111 1111 0101; its decimal representation is _______
A processor can support a maximum memory of 4 GB, where the memory is word-addressable (a word consists of two bytes). The size of…
The data count register of a DMA controller is 16 bits. A file of 29,154 kilobytes needs to be transferred from disk to byte-addre…
Let X be the number of distinct 16-bit integers in 2's complement representation. Let Y be the number of distinct 16-bit integers …
A processor has 40 distinct instructions and 24 general purpose registers. A 32-bit instruction word has an opcode, two register o…
Functions F and G take 5 and 3 ns by units UF and UG, respectively. Given two instances of UF and two of UG, it is required to com…
Free account benefits
Turn practice into measurable progress
Public PYQs and reference pages stay free. Sign in when you want GATEverse to remember what you studied and guide what to practise next.
Saved progressKeep answers, mock results and completion history across devices.
Adaptive practiceGet questions matched to your recent accuracy and difficulty level.
Bookmarks and notesBuild a personal revision list and record why a question was difficult.
Performance insightsSee weak subjects, accuracy trends, streaks and exam readiness.