Consider the following statements: I. Daisy chaining is used to assign priorities in attending interrupts. II. When a device raise…
Consider the following data path diagram. Consider an instruction: R0 <- R1 + R2. The following steps are used to execute it over …
A direct mapped cache memory of 1 MB has a block size of 256 bytes. The cache has an access time of 3 ns and a hit rate of 94%. Du…
Consider three registers R1, R2, and R3 that store numbers in IEEE-754 single precision floating point format. Assume that R1 and …
A computer system with a word length of 32 bits has a 16 MB byte-addressable main memory and a 64 KB, 4-way set associative cache …
Consider a non-pipelined processor operating at 2.5 GHz taking 5 clock cycles per instruction. A 5-stage pipeline version operates…
Free account benefits
Public PYQs and reference pages stay free. Sign in when you want GATEverse to remember what you studied and guide what to practise next.